The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Jul. 31, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Ja-Hyun Koo, Gyeonggi-do, KR;

Jong-Hyun Park, Gyeonggi-do, KR;

Seung-Gyu Jeong, Gyeonggi-do, KR;

Jung-Hyun Kwon, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G06F 12/1009 (2016.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0069 (2013.01); G06F 2212/65 (2013.01);
Abstract

Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (MSB) N bits of a physical address for identifying the cubes; allocating least significant bit (LSB) M bits of the physical address for designating locations of memory cells included in each of the cubes, M and N being positive integers; storing information about a mapping between a logical address and the (M+N)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.


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