The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2018
Filed:
May. 14, 2012
Peter G. Sassone, Austin, TX (US);
Christopher Edward Koob, Round Rock, TX (US);
Dana M. Vantrease, Austin, TX (US);
Suresh K. Venkumahanti, Austin, TX (US);
Lucian Codrescu, Austin, TX (US);
Peter G. Sassone, Austin, TX (US);
Christopher Edward Koob, Round Rock, TX (US);
Dana M. Vantrease, Austin, TX (US);
Suresh K. Venkumahanti, Austin, TX (US);
Lucian Codrescu, Austin, TX (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.