The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Nov. 13, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, Sichuan, CN;

Inventors:

Xiaofei Yang, Beijing, CN;

Yuqing Yang, Beijing, CN;

Yanxia Xin, Beijing, CN;

Zailong Mo, Beijing, CN;

Xue Jiang, Beijing, CN;

Xun Mou, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1339 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13394 (2013.01); G02F 1/1368 (2013.01); G02F 1/13624 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G02F 2001/13398 (2013.01); G02F 2001/134345 (2013.01); G02F 2001/136218 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

An array substrate and a fabrication method thereof and a display device are provided. The array substrate comprises: a base substrate; a plurality of gate lines and a plurality of data lines formed on the base substrate, the plurality of gate lines and the plurality of data lines intersecting with each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode, and the plurality of sub-pixels including a first sub-pixel; a passivation layer formed on the base substrate and covering the gate lines, the data lines and the thin film transistor, a via hole being provided in the passivation layer and the pixel electrode being formed on the passivation layer and connected with a drain electrode or a source electrode of the thin film transistor through the via hole in each of the sub-pixels; and a first spacer, provided in the via hole of the first sub-pixel.


Find Patent Forward Citations

Loading…