The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2018
Filed:
Apr. 14, 2017
Google Inc., Mountain View, CA (US);
Hong Liu, Palo Alto, CA (US);
Ryohei Urata, San Carlos, CA (US);
Woon Seong Kwon, Cupertino, CA (US);
Teckgyu Kang, Saratoga, CA (US);
Google LLC, Mountain View, CA (US);
Abstract
Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.