The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Jul. 20, 2015
Applicant:

Rensselaer Polytechnic Institute, Troy, NY (US);

Inventors:

Tong Zhang, Watervliet, NY (US);

Hao Wang, Hefei, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/15 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/154 (2013.01); G06F 3/064 (2013.01); G06F 3/0611 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01); H03M 13/1575 (2013.01); H03M 13/6502 (2013.01);
Abstract

A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.


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