The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Dec. 31, 2015
Applicant:

Unist (Ulsan National Institute of Science and Technology), Ulsan, KR;

Inventors:

Kyung Rok Kim, Ulsan, KR;

Min Woo Ryu, Ulsan, KR;

Sang Hyo Ahn, Ulsan, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/112 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41758 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/4238 (2013.01); H01L 29/42376 (2013.01); H01L 29/78 (2013.01); H01L 31/1126 (2013.01);
Abstract

A ring-type FET may include a silicon base, a source formed on a portion of the silicon base through doping, a channel formed to encompass the source on a plane, a drain formed outside the channel, a dielectric layer formed on the source, the channel and the drain, and a gate provided on the dielectric layer, wherein a center of the source is spaced apart from a center of the channel, and the gate is formed of a metal material, disposed above the channel and configured to cover an upper face of the channel and overlap a portion of the source and a portion of the drain.


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