The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2018
Filed:
Jul. 11, 2017
Applicant:
Murata Manufacturing Co., Ltd., Nagaokakyo-shi, Kyoto-fu, JP;
Inventors:
Noboru Kato, Nagaokakyo, JP;
Toshiyuki Nakaiso, Nagaokakyo, JP;
Assignee:
MURATA MANUFACTURING CO., LTD., Nagaokakyo-Shi, Kyoto-Fu, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 21/4763 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/60 (2006.01); H01L 23/532 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 23/528 (2013.01); H01L 23/60 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 27/0207 (2013.01); H01L 27/0248 (2013.01); H01L 23/525 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract
The present invention is provided with a Si substrate, an ESD protection circuit formed in the Si substrate, pads formed on the surface of the Si substrate and electrically connected to first and second input/output terminals of the ESD protection circuit, a rewiring layer formed on the surface of the Si substrate for electrically connecting the pads and metal plated films, and an insulating resin film formed on the rear surface of the Si substrate. Thus, provided is an ESD protection device which can suppress the influence of external noise, etc.