The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Jun. 03, 2016
Applicant:

Rf Micro Devices, Inc., Greensboro, NC (US);

Inventors:

Thomas Scott Morris, Lewisville, NC (US);

David Jandzinski, Summerfield, NC (US);

Stephen Parker, Burlington, NC (US);

Jon Chadwick, Greensboro, NC (US);

Julio C. Costa, Oak Ridge, NC (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/29 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/568 (2013.01); H01L 23/29 (2013.01); H01L 23/3135 (2013.01); H01L 23/373 (2013.01); H01L 23/3737 (2013.01); H01L 23/4334 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 25/0655 (2013.01); H01L 21/561 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/10 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/92 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01);
Abstract

The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.


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