The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Apr. 04, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Sang-Ho Lee, Gyeonggi-do, KR;

Kyeong-Tae Kim, Gyeonggi-do, KR;

Jae-Boum Park, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/14 (2006.01); G11C 29/36 (2006.01); G11C 29/08 (2006.01); G11C 29/54 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G11C 29/50 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/36 (2013.01); G11C 29/08 (2013.01); G11C 29/14 (2013.01); G11C 29/38 (2013.01); G11C 29/44 (2013.01); G11C 29/46 (2013.01); G11C 29/50004 (2013.01); G11C 29/54 (2013.01);
Abstract

A test mode setting circuit may include: a first test mode signal generation unit operated by a first supply voltage, and suitable for activating a first test mode signal at a first voltage level in a state where mode setting is being performed, the first test mode signal corresponding to a test code among a plurality of first test mode signals; and a second test mode signal generation unit operated by a second supply voltage, and suitable for latching the first test mode signal at a second voltage level and generating the latched first test mode signal as a second test mode signal even when the first supply voltage is deactivated to a third supply voltage lower than the first supply voltage.


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