The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Mar. 10, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Keisuke Nakatsuka, Seoul, KR;

Tsuneo Inaba, Kamakura Kanagawa, JP;

Yutaka Shirai, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/28 (2006.01); G11C 11/16 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1675 (2013.01); G11C 11/5642 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.


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