The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Dec. 12, 2012
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Alok Gupta, Fremont, CA (US);

Wishwesh Gandhi, Sunnyvale, CA (US);

Ram Gummadi, San Jose, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 8/06 (2006.01); G06F 12/02 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 8/00 (2013.01); G06F 12/0207 (2013.01); G11C 8/06 (2013.01); G11C 7/1075 (2013.01); G11C 2207/105 (2013.01);
Abstract

One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. The technique requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. The technique for accessing non-contiguous locations within a DRAM memory page.


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