The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Mar. 20, 2017
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Vineet Agrawal, San Jose, CA (US);

Roger Bettman, Los Altos, CA (US);

Samuel Leshner, Los Gatos, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/18 (2006.01); G11C 5/14 (2006.01); G06F 12/02 (2006.01); G11C 7/12 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/18 (2013.01); G06F 12/023 (2013.01); G11C 5/147 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); G11C 7/22 (2013.01); G06F 2212/1044 (2013.01);
Abstract

Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.


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