The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2018
Filed:
Jan. 09, 2017
Applicant:
Arm Limited, Cambridge, GB;
Inventors:
Yew Keong Chong, Austin, TX (US);
Andy Wangkun Chen, Austin, TX (US);
Sriram Thyagarajan, Austin, TX (US);
Gus Yeung, Austin, TX (US);
James Dennis Dodrill, Dripping Springs, TX (US);
Assignee:
ARM Limited, Cambridge, GB;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 29/50 (2006.01); G11C 5/14 (2006.01); G11C 8/06 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1012 (2013.01); G11C 5/141 (2013.01); G11C 8/06 (2013.01); G11C 8/18 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 29/50012 (2013.01); G11C 29/702 (2013.01);
Abstract
Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.