The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2018
Filed:
Feb. 19, 2016
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventors:
Seung Bong Kim, Icheon-si, KR;
Geun Il Lee, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 29/00 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 29/816 (2013.01); G11C 29/84 (2013.01); G11C 29/781 (2013.01); G11C 2207/105 (2013.01);
Abstract
A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.