The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2018
Filed:
Sep. 25, 2015
Qualcomm Incorporated, San Diego, CA (US);
Serag Monier GadelRab, Markham, CA;
Jason Edward Podaima, Markham, CA;
Ruolong Liu, Markham, CA;
Alexander Miretsky, Vaughan, CA;
Paul Christopher John Wiercienski, Toronto, CA;
Kyle John Ernewein, Toronto, CA;
Carlos Javier Moreira, Markham, CA;
Simon Peter William Booth, San Diego, CA (US);
Meghal Varia, Brampton, CA;
Thomas David Dryburgh, Markham, CA;
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.