The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

May. 23, 2016
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Arkaprava Basu, Austin, TX (US);

Bradford M. Beckmann, Redmond, WA (US);

Shuai Che, Bellevue, WA (US);

Sooraj Puthoor, Austin, TX (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 12/0837 (2016.01); G06F 12/14 (2006.01); G06F 12/0817 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/0837 (2013.01); G06F 12/0817 (2013.01); G06F 12/1027 (2013.01); G06F 12/1483 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/621 (2013.01); G06F 2212/657 (2013.01);
Abstract

The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.


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