The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Aug. 29, 2016
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Francky Catthoor, Temse, BE;

Praveen Raghavan, Leefdaal, BE;

Matthias Hartmann, Kessel-lo, BE;

Komalan Manu Perumkunnil, Kerala, IN;

Jose Ignacio Gomez, Madrid, ES;

Christian Tenllado, Madrid, ES;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/0811 (2016.01); G06F 3/06 (2006.01); G06F 12/0893 (2016.01); G06F 12/0897 (2016.01); G11C 7/10 (2006.01); G11C 11/16 (2006.01); G06F 15/78 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 3/0611 (2013.01); G06F 3/0656 (2013.01); G06F 3/0685 (2013.01); G06F 3/0688 (2013.01); G06F 12/0893 (2013.01); G06F 12/0897 (2013.01); G11C 7/10 (2013.01); G11C 11/165 (2013.01); G06F 13/1657 (2013.01); G06F 13/1673 (2013.01); G06F 15/781 (2013.01); G06F 15/7846 (2013.01); G06F 2212/222 (2013.01); G06F 2212/454 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01);
Abstract

The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level, referred to as L, memory structure comprising a non-volatile memory unit as Ldata memory and a buffer structure (L-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the Ldata memory and the buffer structure (L-VWB) by the processor.


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