Bank address remapping to load balance memory traffic among banks of memory

Abstract

A system includes a processing component and a memory controller. The memory controller is to conduct memory accesses to a banked memory responsive to memory access requests from the processing component, whereby the memory controller is to distribute memory accesses among the plurality of banks by modifying, for each memory access request, a bank of the bank memory referenced by the memory access request. A memory device includes a plurality of banks, an interface to receive memory access requests, bank remapping logic, and access control logic. The bank remapping logic is to, for each received memory access request, remap a bank segment of a memory address associated with the received memory access request with a modified bank segment. The access control logic is to, for each received memory access request, access a bank of the plurality of banks based on the modified bank segment for the memory access request.