The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Jan. 13, 2014
Applicant:

United Technologies Corporation, Hartford, CT (US);

Inventors:

Michael Hrach, West Hartford, CT (US);

Andrew Brehm, West Hartford, CT (US);

Assignee:

United Technologies Corporation, Farmington, CT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 13/00 (2006.01); G05D 7/00 (2006.01); G06F 19/00 (2018.01); F02C 9/18 (2006.01); F02C 9/00 (2006.01); F02C 9/28 (2006.01); F02C 9/26 (2006.01); G05B 15/02 (2006.01); H03H 7/01 (2006.01); G05B 9/03 (2006.01);
U.S. Cl.
CPC ...
F02C 9/18 (2013.01); F02C 9/00 (2013.01); F02C 9/263 (2013.01); F02C 9/28 (2013.01); G05B 9/03 (2013.01); G05B 15/02 (2013.01); H03H 7/01 (2013.01); F05D 2200/14 (2013.01); F05D 2200/33 (2013.01); F05D 2220/32 (2013.01); F05D 2240/20 (2013.01); F05D 2240/35 (2013.01); F05D 2260/84 (2013.01); F05D 2260/96 (2013.01); F05D 2270/101 (2013.01); F05D 2270/301 (2013.01); F05D 2270/309 (2013.01); F05D 2270/54 (2013.01); F05D 2270/70 (2013.01);
Abstract

A filter algorithm for a dual channel electronic engine control system according to one disclosed non-limiting embodiment of the present disclosure includes a division function that divides a measured pressure rate of change of one of a FADEC channel A and FADEC channel B by an average pressure of the FADEC channel A and the FADEC channel B to obtain a resultant value; a first comparator function to bound a proper high resultant value from the division function; a second comparator function to bound a proper low resultant value from the division function; and an OR gate in communication with the first comparator and the second comparator such that if an output from either the first comparator function and the second comparator function is true, that one of the FADEC channel A and the FADEC channel B is filtered out for a time period.


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