The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2018
Filed:
Sep. 18, 2017
Invecas, Inc., Santa Clara, CA (US);
Narasimhan Vasudevan, San Diego, CA (US);
Venkata N. S. N. Rao, Fremont, CA (US);
Prasad Chalasani, San Jose, CA (US);
Invecas, Inc., Santa Clara, CA (US);
Abstract
A master-slave delay locked loop system comprises a master delay locked loop ('MDLL') for generating at least one bias voltage and at least one slave delay locked loop ('SDLL'). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.