The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Feb. 20, 2015
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Kent R. Townley, San Jose, CA (US);

Christopher D. Ebeling, San Jose, CA (US);

Hamish Fallside, Monte Sereno, CA (US);

Prasun K. Raha, Palo Alto, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); H04L 7/00 (2006.01); H03L 7/00 (2006.01); H03K 19/177 (2006.01); G06F 1/10 (2006.01); G06F 1/06 (2006.01); G06F 1/04 (2006.01); H03K 19/173 (2006.01); G06F 1/08 (2006.01); G06F 17/50 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17796 (2013.01); G06F 1/04 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); H03K 19/173 (2013.01); H03K 19/1733 (2013.01); H03K 19/17728 (2013.01); H03K 19/17736 (2013.01); G06F 17/5045 (2013.01); G06F 17/5054 (2013.01); H03K 19/00 (2013.01); H03K 19/177 (2013.01); H03K 19/1774 (2013.01);
Abstract

A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.


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