The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Jul. 25, 2017
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventor:

Koji Maruyama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H02M 7/00 (2006.01); H02M 7/537 (2006.01); H01L 25/11 (2006.01);
U.S. Cl.
CPC ...
H02M 7/003 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/115 (2013.01); H02M 7/537 (2013.01);
Abstract

A power converter in which a plurality of semiconductor switches are connected to a plurality of drive circuits configured to control states of the semiconductor switches includes a first semiconductor switch, a second semiconductor switch, a first drive circuit, a second drive circuit, and a multilayer substrate in which a first wiring, and a second wiring are disposed. In the multilayer substrate, a reference potential wiring and a control signal wiring of the first wiring are disposed in different layers at positions overlapping in a substrate lamination direction, a reference potential wiring and a control signal wiring of the second wiring are disposed in different layers at positions overlapping in the lamination direction, and a wiring length of a portion in which the first wiring and the second wiring overlap in the lamination direction is set to be shorter than either a wiring length of a portion in which the reference potential wiring and the control signal wiring of the first wiring overlap in the lamination direction or a wiring length of a portion in which the reference potential wiring and the control signal wiring of the second wiring overlap in the lamination direction.


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