Tapered polysilicon gate layout for power handling improvement for radio frequency (rf) switch applications

Abstract

A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel regions. The polysilicon gate structure also includes a polysilicon base region that connects first ends of the polysilicon gate fingers. The polysilicon gate structure also includes triangular polysilicon extension regions coupled to the polysilicon gate fingers. The triangular extension regions can be located at the first ends of the polysilicon gate fingers (abutting the polysilicon base region), or at second (opposing ends) of the polysilicon gate fingers.