IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10014320 B1

PDFFull Text
Date of Patent:
Jul. 03, 2018

Filed:

Aug. 25, 2016

Semiconductor integrated circuit device

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yusuke Kanno, Kodaira, JP;

Hiroyuki Mizuno, Musashino, JP;

Yoshihiko Yasu, Kodaira, JP;

Kenji Hirose, Tokorozawa, JP;

Takahiro Irita, Kodaira, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Shapiro, Gabor and Rosenberger, PLLC

Primary Examiner:

Stacy Whitmore

Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/11 (2006.01); H01L 23/50 (2006.01); H01L 27/02 (2006.01); H03K 3/03 (2006.01); H01L 27/118 (2006.01); H03K 3/037 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H03K 17/16 (2006.01); G11C 11/419 (2006.01); H01L 27/00 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11898 (2013.01); G06F 17/5068 (2013.01); G11C 11/419 (2013.01); H01L 23/48 (2013.01); H01L 23/50 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H03K 3/0315 (2013.01); H03K 3/0375 (2013.01); H03K 17/16 (2013.01); G06F 17/5072 (2013.01); H01L 27/00 (2013.01); H01L 27/02 (2013.01); H01L 27/0203 (2013.01); H01L 29/7835 (2013.01); H01L 2027/11881 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Find Patent Forward Citations

Loading…