The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Dec. 07, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

YiPeng Chan, Shanghai, CN;

Jieqiong Dong, Shanghai, CN;

Huajun Jin, Shanghai, CN;

Ruling Zhou, Shanghai, CN;

Shibi Guo, Shanghai, CN;

Bongkil Kim, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/15 (2006.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/11524 (2017.01); H01L 27/11536 (2017.01); H01L 27/11539 (2017.01); H01L 27/11541 (2017.01); H01L 27/11543 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 27/11524 (2013.01); H01L 27/11536 (2013.01); H01L 27/11539 (2013.01); H01L 27/11541 (2013.01); H01L 27/11543 (2013.01); H01L 29/42324 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.


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