Integrated circuits, methods and interface circuitry to synchronize data transfer between high and low speed clock domains

Abstract

Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.