The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Mar. 07, 2016
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Min Su Park, Seoul, KR;

Jin Hee Cho, Cheongju-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 7/14 (2006.01); G11C 11/56 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/1048 (2013.01); G11C 29/52 (2013.01); G11C 7/14 (2013.01); G11C 11/5642 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Provided are a semiconductor device including an error correction code circuit and a driving method thereof. The semiconductor device includes a plurality of normal mats including a plurality of memory cells and connected to data lines, a plurality of dummy mats arranged in specific areas of the plurality of normal mats and inputting/outputting parity bits through parity lines of a specific circuit, a plurality of free ECC (Error Correction Code) calculation circuits that perform ECC calculation corresponding to data applied through the data lines and the parity lines, and a main ECC calculation circuit that combines data applied from the plurality of free ECC calculation circuits with one another and performs ECC calculation.


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