The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Dec. 02, 2016
Applicant:

Multek Technologies Limited, San Jose, CA (US);

Inventors:

Joan K. Vrtis, Mesa, AZ (US);

Michael James Glickman, Mountain View, CA (US);

Todd Robinson, San Mateo, CA (US);

Hollese Galyon, Beaverton, OR (US);

Assignee:

Multek Technologies Limited, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0201 (2013.01); H05K 1/0271 (2013.01); H05K 1/0298 (2013.01); H05K 1/111 (2013.01); H05K 1/115 (2013.01); H05K 3/4602 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H05K 1/181 (2013.01); H05K 2201/068 (2013.01);
Abstract

A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.


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