The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2018
Filed:
May. 24, 2013
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 4/00 (2009.01); H04W 72/08 (2009.01); H04W 72/12 (2009.01); H04W 52/50 (2009.01); H04B 17/327 (2015.01); H04W 72/04 (2009.01); H04W 52/24 (2009.01); H04B 17/309 (2015.01);
U.S. Cl.
CPC ...
H04W 72/082 (2013.01); H04B 17/327 (2015.01); H04W 52/50 (2013.01); H04W 72/0406 (2013.01); H04W 72/1226 (2013.01); H04B 17/309 (2015.01); H04W 52/242 (2013.01); H04W 52/244 (2013.01);
Abstract
Interference mitigation solutions are disclosed for interference experienced based on asymmetric uplink (UL)/downlink (DL) slot configuration. The aggressor/victim network entities are identified using either measurement or static/semi-static means, such that the victim network entities that may be impacted by interference from aggressor network entity transmissions are identified. Inter Cell Interference Coordination (ICIC) mechanisms are extended to negotiate and address scheduling that intelligently mitigates interference that occurs in the colliding slots.