The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2018
Filed:
Mar. 31, 2017
Applicant:
Nvidia Corporation, Santa Clara, CA (US);
Inventors:
Andreas J. Gotterba, Santa Clara, CA (US);
Jesse S. Wang, Santa Clara, CA (US);
Assignee:
NVIDIA Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 3/038 (2006.01); H03K 19/094 (2006.01); G11C 11/419 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0002 (2013.01); G11C 7/065 (2013.01); G11C 11/419 (2013.01); H03K 3/038 (2013.01); H03K 19/09425 (2013.01);
Abstract
Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n−1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.