The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Jul. 11, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Thomas J. Brunschwiler, Thalwil, CH;

Andreas Christian Doering, Zufikon, CH;

Ronald Peter Luijten, Thalwil, CH;

Stefano Sergio Oggioni, Milan, IT;

Patricia Maria Sagmeister, Adliswil, CH;

Martin Leo Schmatz, Rueschlikon, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/3114 (2013.01); H01L 23/367 (2013.01); H01L 23/49838 (2013.01); H01L 24/48 (2013.01); H01L 2224/48225 (2013.01);
Abstract

Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.


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