The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Jun. 16, 2015
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Kosuke Hareyama, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 21/48 (2006.01); H01L 23/49 (2006.01); H01L 25/18 (2006.01); H01P 3/08 (2006.01); H01P 11/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 25/18 (2013.01); H01P 3/081 (2013.01); H01P 11/003 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6627 (2013.01);
Abstract

The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of realizing impedance control of the semiconductor device. An input/output wiring lineand a ground wiring lineare such that through glass vias are provided so as to form a strip line structure by blasting or electric discharge machining and thereafter metal films are formed on a surface and a rear surface. It is possible to configure the semiconductor device with the impedance control by adjusting a conductor diameter of the input/output wiring lineand an insulating layer thickness between the input/output wiring lineand the ground wiring line. The present technology may be applied to the semiconductor device.


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