The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2018
Filed:
Oct. 16, 2017
Applicant:
Richard K Williams, Cupertino, CA (US);
Inventor:
Richard K Williams, Cupertino, CA (US);
Assignee:
Adventive IPBank, Luxembourg, LU;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H05K 5/02 (2006.01); H05K 7/18 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49805 (2013.01); H01L 21/4828 (2013.01); H01L 21/4842 (2013.01); H01L 23/49861 (2013.01); H01L 24/48 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48108 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48464 (2013.01);
Abstract
In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as 'wave soldering' that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad.