The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Mar. 28, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Siamak Fazelpour, San Diego, CA (US);

Charles David Paynter, Encinitas, CA (US);

Ryan David Lane, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 5/00 (2006.01); H01F 27/28 (2006.01); H01F 17/00 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01F 17/0013 (2013.01); H01L 23/49822 (2013.01); H01F 2017/002 (2013.01); H01F 2017/0066 (2013.01); H01L 23/49827 (2013.01); H01L 23/645 (2013.01); H01L 28/10 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3011 (2013.01);
Abstract

Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.


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