The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Sep. 20, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jason Edward Podaima, Toronto, CA;

Paul Christopher John Wiercienski, Toronto, CA;

Carlos Javier Moreira, Markham, CA;

Alexander Miretsky, Vaughan, CA;

Meghal Varia, Brampton, CA;

Kyle John Ernewein, Toronto, CA;

Manokanthan Somasundaram, Markham, CA;

Muhammad Umar Choudry, Markham, CA;

Serag Monier Gadelrab, Markham, CA;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/08 (2016.01); G06F 12/1045 (2016.01); G06F 12/0891 (2016.01); G06F 12/0844 (2016.01); G06F 12/1036 (2016.01); G06F 12/0806 (2016.01); G06F 12/0842 (2016.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1063 (2013.01); G06F 12/0844 (2013.01); G06F 12/0891 (2013.01); G06F 12/1036 (2013.01); G06F 12/0806 (2013.01); G06F 12/0842 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/50 (2013.01); G06F 2212/655 (2013.01); G06F 2212/682 (2013.01); G06F 2212/683 (2013.01); G06F 2212/684 (2013.01);
Abstract

Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.


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