The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Sep. 06, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventor:

Kirk D. Lamb, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0871 (2016.01); G06F 12/06 (2006.01); G06F 11/30 (2006.01); G06F 12/0866 (2016.01); G06F 3/06 (2006.01); G06F 12/0804 (2016.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G06F 11/3055 (2013.01); G06F 12/0638 (2013.01); G06F 12/0804 (2013.01); G06F 12/0866 (2013.01); G06F 12/0868 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/312 (2013.01); G06F 2212/604 (2013.01); Y02D 10/13 (2018.01);
Abstract

Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer program product for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a transfer logic used in a power-loss save of the write cache. The one or more operating parameters include an instance-specific process speed of the transfer logic which is retrieved as bin data. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.


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