The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Dec. 18, 2015
Applicant:

Microsemi Solutions (U.s.), Inc., Aliso Viejo, CA (US);

Inventors:

Stephen Bates, Canmore, CA;

Rahul Advani, Los Gatos, CA (US);

Assignee:

Microsemi Solutions (U.S.), Inc., Aliso Viejo, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 11/5621 (2013.01); G11C 16/0483 (2013.01); G06F 2212/7206 (2013.01); G11C 2211/5641 (2013.01);
Abstract

A solid-state storage device (SSD) controller is provided for use with an SSD. The SSD includes a plurality of memory cells, such as non-volatile memory (NVM) cells. The SSD controller comprises a processor and a memory storing statements and instructions for execution by the processor to perform a method of configuring the memory cells. In a dynamic configuration implementation in which at least a subset of the NVM cells are configured in a first bit retention mode, the method includes: monitoring data activity in relation to the SSD; and dynamically reconfiguring the subset of the NVM cells in a second bit retention mode based on the monitored data activity, such as whether data traffic comprises a majority of read activity or write activity. In a static configuration implementation, the method includes receiving at least one performance characteristic for the NVM cells; and configuring the subset of the NVM cells in a first bit retention mode based on the received at least one performance characteristic.


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