The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2018
Filed:
Oct. 21, 2014
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Navid Ehsan, San Diego, CA (US);
Praveen Appu, San Diego, CA (US);
Raghu Narayan Challa, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); H04W 52/02 (2009.01);
U.S. Cl.
CPC ...
G06F 1/3206 (2013.01); G06F 1/324 (2013.01); G06F 1/3234 (2013.01); G06F 1/3296 (2013.01); H04W 52/029 (2013.01); H04W 52/0229 (2013.01); H04W 76/28 (2018.02); Y02D 70/00 (2018.01); Y02D 70/1242 (2018.01); Y02D 70/1262 (2018.01); Y02D 70/142 (2018.01); Y02D 70/146 (2018.01); Y02D 70/23 (2018.01); Y02D 70/24 (2018.01); Y02D 70/25 (2018.01);
Abstract
A method for power optimization by an apparatus is disclosed. The method includes identifying one or more network parameters that affect one or more of a processing rate and a power usage of the processor in a connected state. The method also includes identifying a trigger event for the one or more network parameters. The method further includes adjusting a performance of the processor in the connected state when the trigger event occurs.