The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2018

Filed:

Mar. 22, 2017
Applicants:

Phil Ouk Nam, Suwon-si, KR;

Hyung Joon Kim, Yongin-si, KR;

Sung Gil Kim, Yongin-si, KR;

Ji Hoon Choi, Seongnam-si, KR;

Seulye Kim, Seoul, KR;

Hong Suk Kim, Yongin-si, KR;

Jae Young Ahn, Seongnam-si, KR;

Inventors:

Phil Ouk Nam, Suwon-si, KR;

Hyung Joon Kim, Yongin-si, KR;

Sung Gil Kim, Yongin-si, KR;

Ji Hoon Choi, Seongnam-si, KR;

Seulye Kim, Seoul, KR;

Hong Suk Kim, Yongin-si, KR;

Jae Young Ahn, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 29/40 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/0653 (2013.01); H01L 29/402 (2013.01); H01L 29/408 (2013.01);
Abstract

A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.


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