The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2018

Filed:

Aug. 02, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Michael James Solimando, San Diego, CA (US);

William Stone, San Diego, CA (US);

John Holmes, San Diego, CA (US);

Christopher Healy, San Diego, CA (US);

Rajendra Pendse, San Diego, CA (US);

Sun Yun, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/02 (2006.01); H01L 25/065 (2006.01); H01L 21/54 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/4882 (2013.01); H01L 21/54 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/367 (2013.01); H01L 23/3672 (2013.01); H01L 23/49827 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01);
Abstract

A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.


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