The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2018
Filed:
Dec. 14, 2016
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Yoshiyuki Abe, Tokyo, JP;
Chuichi Miyazaki, Tokyo, JP;
Hideo Mutou, Tokyo, JP;
Tomoko Higashino, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/268 (2006.01); H01L 21/683 (2006.01); H01L 21/304 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/67 (2006.01); H01L 25/065 (2006.01); B23K 26/00 (2014.01); B23K 26/53 (2014.01); B23K 101/40 (2006.01); B23K 103/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); B23K 26/0006 (2013.01); B23K 26/0057 (2013.01); B23K 26/53 (2015.10); H01L 21/268 (2013.01); H01L 21/304 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/67092 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 23/544 (2013.01); H01L 25/065 (2013.01); B23K 2201/40 (2013.01); B23K 2203/56 (2015.10); H01L 2221/68327 (2013.01); H01L 2223/5446 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01);
Abstract
To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.