The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2018
Filed:
May. 04, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/11 (2006.01); H01L 21/3115 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76825 (2013.01); H01L 21/31155 (2013.01); H01L 21/76805 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01);
Abstract
Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.