The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2018
Filed:
Jun. 10, 2015
Applicant:
Microchip Technology Incorporated, Chandler, AZ (US);
Inventors:
Justin Hiroki Sato, West Linn, OR (US);
Andrew Alexander Taylor, Portland, OR (US);
Assignee:
MICROCHIP TECHNOLOGY INCORPORATED, Chandler, AZ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76813 (2013.01); H01L 21/76807 (2013.01); H01L 21/76843 (2013.01); H01L 21/76871 (2013.01); H01L 2221/1031 (2013.01);
Abstract
A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.