The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2018
Filed:
Apr. 19, 2016
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Haeng Seon Chae, Yongin-si, KR;
Assignee:
SK hynix Inc., Icheon-si Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/46 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/14 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G01R 31/3177 (2013.01); G01R 31/31701 (2013.01); G01R 31/31723 (2013.01); G11C 29/00 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/14 (2013.01); G11C 29/56012 (2013.01); G11C 2029/1208 (2013.01);
Abstract
A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.