Shift register unit, gate driving circuit and driving method, and display apparatus

Abstract

The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK/CLK, a second bias-control terminal to receive a second/first bias signal CLK/CLK, and a first control level terminal provided with a first control voltage VC, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK/CLK, a fourth bias-control terminal to receive a fourth/third bias signal CLK/CLK, and a second control level terminal provided with a second control voltage VC; configuring the first bias signal CLKand the second bias signal CLKas first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VCto a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLKand the fourth bias signal CLKto a turn-off level and the second control voltage VCto turn-on level during the first sub-cycle; configuring the third bias signal CLKand the fourth bias signal CLKas second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VCto a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLKand the second bias signal CLKto a turn-off level and the second control voltage VCto a turn-on level during the second sub-cycle.