Optimizing shading process for mixed order-sensitive and order-insensitive shader operations

Abstract

A graphics processing unit (GPU) includes programmable shader hardware and grouping hardware. The grouping hardware receives pixels collected from a set of primitives, wherein pixel locations of each primitive have been obtained through rasterization of a set of vertices of the primitive. The grouping hardware also groups the pixels into a set of groups having a sequential order. None of the pixels in each group overlapped with each other in a display and overlapped pixels belong to different groups. The programmable shader hardware performs order-insensitive shader operations on the groups according to a first subset of an instruction set defined for a programmable shader, with two or more of the groups processed in parallel. The programmable shader hardware also performs order-sensitive shader operations on each of the groups in the sequential order according to a second subset of the instruction set defined for the programmable shader.