The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2018

Filed:

Mar. 09, 2016
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Bryan Kris, Gilbert, AZ (US);

Igor Wojewoda, Tempe, AZ (US);

Alex Dumais, Gilbert, AZ (US);

Mike Catherwood, Georgetown, TX (US);

Brian Fall, Mesa, AZ (US);

Jason Tollefson, Phoenix, AZ (US);

Calum Wilke, Chandler, AZ (US);

Dave Mickey, Chandler, AZ (US);

Thomas Spohrer, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 3/00 (2006.01); G06F 13/42 (2006.01); G06F 13/364 (2006.01); G06F 13/16 (2006.01); G06F 15/78 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 13/1673 (2013.01); G06F 13/364 (2013.01); G06F 13/385 (2013.01); G06F 15/7807 (2013.01); Y02D 10/12 (2018.01); Y02D 10/13 (2018.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.


Find Patent Forward Citations

Loading…