The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2018

Filed:

Nov. 12, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Hyun Seok Cha, Osan-si, KR;

Yong Tae Jeon, Pohang-si, KR;

Ki Chul Noh, Suwon-si, KR;

Ki Jo Jung, Gwacheon-si, KR;

Chandrashekar Tandavapura Jagadish, Mysore, IN;

Vamshi Krishna Komuravelli, Telangana, IN;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01);
Abstract

A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.


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