Graphics processing systems

Abstract

A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to the rendered fragment data being written out to memory, write out circuitry configured to write a compressed representation of the rendered fragment data for a tile in the tile buffer to memory, and processing circuitry. The processing circuitry identities, based on the writing of rendered fragment data to the tile buffer, any blocks comprising sampling positions within a tile having the same data value associated with each sampling position in the block, and to, when such a block of sampling positions is identified, trigger the write out circuitry to write a compressed representation of the block to the memory.