Hitachi Global Storage Technologies Netherlands B.v.

Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

California Institute of Technology

Sandisk Technologies Inc.

Hitachi Global Storage Technologies

Other

Zvonimir Z Bandic

Cyril Guyot

Robert Eugeniu Mateescu

Thomas R Albrecht

Qingbo Wang

Luiz M Franca-Neto

Dejan Vucinic

Minghai Qin

Seung-Hwan Song

Kiran Kumar Gunnam

Jordan Asher Katine

Won Ho Choi

Anand Kulkarni

Bruce Alexander Wilson

Marco Sanvido

Neil Leslie Robertson

Jui-lung Li

Frank R Chu

Jay Kumar

Jeffery Robinson Childress

Chao Sun

Timothy Tsai

Tsai-Wei Wu

Jorge Campello De Souza

Luis Vitorio Cargnini

Thomas C McGill

Hessam Mahdavifar

Tomohiro Harayama

Eric C Piquette

Bernhard E Knigge

Henry Hung Yang

Michael Anthony Moser

Michael Joseph Rooks

Yongjune Kim

Shad Henry Thorstenson

Yuval Cassuto

Thomas Robert Berthold

Quang Le

Kim Yang Lee

Ernesto Esteban Marinero

A David Erpelding

Olav Hellwig

Elizabeth Ann Dobisz

Xiao Z Wu

Richard M H New

Charles Mathew Mate

Adam Manzanares

Gabriel Zeltzer

Damien Cyril Daniel Le Moal

Martin Chen

Toshiki Hirano

Erhard Theodor Schreck

Ward M Parkinson

Jonathan Darrel Coker

Kurt A Rubin

Takaki Nakamura

James E O'Toole

Bruno Jean Marchon

Hitoshi Kamei

Fu-Ying Huang

Tetsuo Semba

Martin Lueker-Boden

Ashwin Narasimha

Viacheslav Anatolyevich Dubeyko

Donald Joseph Molaro

Adam Michael Espeseth

Abhishek Dhanda

Robert Nolan Payne

Jia-Yang Juang

Ken Qing Yang

Thomas Cocotis

Filip Blagojevic

Dongyang Li

Jaco Hofmann

Vikram Varadarajan Kalkunte

Matheus Almeida Ogleari

Noah Watkins

Certain aspects of the present disclosure provide techniques for partitioning feature maps to improve machine learning model processing. In one aspect, a method, includes partitioning a feature map row-wise into a plurality of feature sub-maps such that: each respective feature sub-map of the plurality of feature sub-maps is defined with respect to a split row determined based on a dense data element count for each row of the feature map; and each feature sub-map of the plurality of feature sub-maps has a same column dimensionality as the feature map; and assigning each of the plurality of feature sub-maps to one of a plurality of tensor compute units and one of a plurality of tensor feature map memory units for processing in parallel.

Just-in-time re-partitioning of feature maps for efficient balancing of compute core workloads

A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.

Memory prefetch based on machine learning

An apparatus includes a tensor compute cluster having a plurality of tensor compute units to process a plurality of sub-feature maps in a machine learning application and a tensor memory cluster having a plurality of tensor feature map memory units to store the plurality of sub-feature maps. The apparatus also includes circuitry to partition an input feature map into the plurality of sub-feature maps such that sparsity in each of the plurality of sub-feature maps satisfies a predetermined threshold, and assign each of the plurality of sub-feature maps to one of the plurality of tensor compute units and one of the plurality of tensor feature map memory units for processing in parallel.

Flexible accelerator for sparse tensors in convolutional neural networks

An apparatus includes a first tensor compute cluster configured to receive first input feature tensors, a second tensor compute cluster configured to receive second input feature tensors more sparse than the first input feature tensors, and a vector accelerator. The apparatus also includes circuitry configured to partition an input feature map into a plurality of input feature tensors based on a compression criteria and assign each of the plurality of input feature tensors to one of the first tensor compute cluster, the second tensor compute cluster, or the vector accelerator based upon at least one of parameters including a sparsity and an optimization parameter.

Flexible accelerator for sparse tensors (FAST) in machine learning

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

Fabric interconnection for memory banks based on network-on-chip methodology

A system with a multiplication circuit having a plurality of multipliers is disclosed. Each of the plurality of multipliers is configured to receive a data value and a weight value to generate a product value in a convolution operation of a machine learning application. The system also includes an accumulator configured to receive the product value from each of the plurality of multipliers and a register bank configured to store an output of the convolution operation. The accumulator is further configured to receive a portion of values stored in the register bank and combine the received portion of values with the product values to generate combined values. The register bank is further configured to replace the portion of values with the combined values.

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

Apparatus, systems, methods, and computer program products for managing refresh operations in memory devices are disclosed. An apparatus includes a memory device including a plurality of memory cells comprising an associated set of counters and a controller for the memory device. A controller is configured to randomly increment a counter associated with a memory cell in response to write disturbances for the memory cell. A controller is configured, in response to a counter being randomly incremented to a predetermined count, perform a refresh operation on a memory cell.

Managing refresh operations for a memory device

Apparatuses, systems, methods, and computer program products are disclosed for memory array addressing. An addressing circuit is configured to receive an address for an operation on an array of multiple memory regions. An address includes a row address and a column address both multiplexed into the address and received with an activate command for an operation. A row buffer for an array of multiple memory regions is configured to store data identified by multiplexed row and column addresses from the multiple memory regions. Data of an operation is selected from a row buffer based on a second address received with a subsequent command for the operation.

Cross-point memory array addressing

A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.

Data reliability information in a non-volatile memory device

A method may include writing data to a hard drive. In some examples, the method may include receiving, by an extent allocator module, a command to write data. The command may include data and a logical block address (LBA) specified by the host. The method may also include mapping, by the extent allocator module, the LBA specified by the host to a drive LBA. The method may further include sending, from the extent allocator module, a command to write the data at the drive LBA.

Logical block address mapping for hard disk drives

The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

Cell-level realization of burn after reading for NAND flash

In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.

Data mapping enabling fast read multi-level 3D NAND to improve lifetime capacity

NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.

Error mitigation for 3D NAND flash memory

Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L&#x2212;1 program states.

Method and apparatus for low-latency read of flash storage devices using fractional bits per cell

Growing community of inventors

San Jose, CA, United States of America

Zvonimir Z Bandic